----------------------------------------------------------------------
-- Delay of N registers (shift register)
-- Stephen West, James Carroll
-- BYU ECEn 620, October 2008
----------------------------------------------------------------------
Library ieee;
	use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;
	
entity Delay is
	generic(
		delay:integer:=1
	);
	port(
		clk, input :in std_logic;
		output: out std_logic
	);
end entity;

architecture Delay of Delay is
	signal delay_n: std_logic_vector( delay downto 0);
begin
	--assert delay<1 report "Delay<1; not allowed!" severity error;
	delay_n(0)<=input;
	delay_loop: for N in 1 to delay generate
		process(clk, delay_n(N))
		begin
			if clk'event and clk='1' then
				delay_n(N)<=delay_n(N-1);
			end if;
		end process;
	end generate;
	output<=delay_n(delay);
end architecture;

